As is well known, a solid state drive (SSD) is a data storage device that uses a non-volatile memory as main storage elements to store data. After data are written to the non-volatile memory, if no power is supplied to the system, the data are still retained in the solid state drive.
FIG. 1 is a schematic functional block diagram illustrating a system with a solid state drive according to the prior art. As shown in FIG. 1, the system 100 comprises a solid state drive 10 and a host device 12. The solid state drive 10 is used for storing data. The host device 12 is in communication with the solid state drive 10. The solid state drive 10 comprises a controlling circuit 101, a cache memory 107 and a non-volatile memory 105. The controlling circuit 101 is in communication with the host device 12 through an external bus 20. Consequently, commands and data can be exchanged between the controlling circuit 101 and the host device 12. Generally, the external bus 20 is a USB bus, an SATA bus, a PCIe bus, or the like. The cache memory 107 is for example a volatile memory such as a dynamic random access memory (DRAM). For example, the storage capacity of the cache memory 107 is 4M byte or 8M byte.
Generally, the cache memory 107 is a data buffer for temporarily storing the write data which is inputted through the host device 12 or temporarily storing the read data which is outputted from the non-volatile memory 105. In case that the host device 12 intends to store the write data into the non-volatile memory 105, the write data received through the external bus 20 is temporarily stored into the cache memory 107 by the controlling circuit 101, and then the write data is transmitted from the cache memory 107 to the non-volatile memory 105 by the controlling circuit 101. Similarly, in case that the host device 12 intends to read the read data from the non-volatile memory 105, the read data from the non-volatile memory 105 is temporarily stored into the cache memory 107 by the controlling circuit 101, and then the read data is transmitted from the cache memory 107 to the host device 12 by the controlling circuit 101.
Another function of the cache memory 107 is to store a flash translation layer table (FTL table). In the solid state drive 10, the controlling circuit 101 can quickly access the data of the non-volatile memory 105 through the FTL table. The function of the non-volatile memory 105 will be illustrated in more details as follows.
Generally, the host device 12 defines the data addresses of the solid state drive 10 through logical block addresses (LBAs). Moreover, the non-volatile memory 105 defines the data addresses of the non-volatile memory 105 through physical allocation addresses (PAAs). Consequently, the solid state drive 10 should have a FTL table for performing data address mapping. The FTL table is stored in the cache memory 107.
For example, when a write command or a read command issued from the host device 12 is received by the controlling circuit 101, a LBA is also issued from the host device 12 to indicate the address of the data to be read or written. After the LBA is received by the controlling circuit 101, the LBA has to be mapped to the corresponding PAA through the FTL table. That is, the LBA is converted into the corresponding PAA by the controlling circuit 101 according to the FTL table. Consequently, the PAA to be read from or written into the non-volatile memory 105 can be realized, and the write data is stored into the corresponding PAA of the non-volatile memory 105 or the read data is read from the corresponding PAA of the non-volatile memory 105.
Generally, in case that electric power is normally supplied to the solid state drive 10, the FTL table is stored in the cache memory 107, so that the corresponding PAA can be quickly read, stored and updated. Before the electric power supplied to the solid state drive 10 is stopped, the FTL table is written to the non-volatile memory 105 by the controlling circuit 101. After the electric power is no longer supplied to the solid state drive 10, the FTL table stored in the cache memory 107 is deleted.
As mentioned above, the FTL table has been written to the non-volatile memory 105 before the electric power supplied to the solid state drive 10 is stopped. Consequently, when the solid state drive 10 is powered by the electric power again, the FTL table in the non-volatile memory 105 is stored into the cache memory 107 again by the controlling circuit 101. Accordingly, the solid state drive 10 can be normally operated. However, the above architecture is not cost-effective.
Therefore, there is a need of simplifying the solid state drive so as to reduce the fabricating cost.